Presentation 1997/6/19
Design of a 24-bit Low-Power RISC Controller for a Single MPEG2 Motion Picture Encoder
T. Enomoto, T. Satoh, H. Iwata, A. Hirobe,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A low power 24bit RISC controller, which is integrated on a single chip MPEG2-MP@ML encoder LSI has been designed. Low power techniques developed for the RISC will be described in detail. The RISC controls data rate for bit-streams and supplies various encoding information to functional blocks. It also controls functional block operation and transfers various data between functional blocks. An instruction set consists of 5 instructions for block-starting/data-supplying, 6 instructions for controlling data transferring between blocks, a power saving instruction that stops the RISC itself, in addition to conventional RISC instructions. The 24bit RISC designed with 0.5μm CMOS rule consumes 140mW and operates 40.5MHz at power supply of 2.5V. The 24bit RISC designed with 0.25μm GaAs rule operates at 500MHz on 0.5V consuming about 1W.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) video signal / encoder / MPEG / RISC / controller / power dissipation / CMOS / GaAs
Paper # ED97-49
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Conference Date 1997/6/19(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of a 24-bit Low-Power RISC Controller for a Single MPEG2 Motion Picture Encoder
Sub Title (in English)
Keyword(1) video signal
Keyword(2) encoder
Keyword(3) MPEG
Keyword(4) RISC
Keyword(5) controller
Keyword(6) power dissipation
Keyword(7) CMOS
Keyword(8) GaAs
1st Author's Name T. Enomoto
1st Author's Affiliation Department of Information & System Engineering Faculty of Science & Engineering Chuo University()
2nd Author's Name T. Satoh
2nd Author's Affiliation Department of Information & System Engineering Faculty of Science & Engineering Chuo University
3rd Author's Name H. Iwata
3rd Author's Affiliation Department of Information & System Engineering Faculty of Science & Engineering Chuo University
4th Author's Name A. Hirobe
4th Author's Affiliation Department of Information & System Engineering Faculty of Science & Engineering Chuo University
Date 1997/6/19
Paper # ED97-49
Volume (vol) vol.97
Number (no) 110
Page pp.pp.-
#Pages 9
Date of Issue