| Presentation | 1997/6/19 Circuit Techniques for 0.5V Single Power Supply Operated Devices Toru Iwata, Yutaka Terada, Hironori Akamatsu, Akira Matsuzawa, Hiroyuki Yamauchi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper present "Gate-Over-Driving CMOS (GO-CMOS) Architecture" for sub-1V operation. The key feature are as follows, (1) instead of using a very low Vt (-0.1V or less) for all transistors, the power supply voltage is boosted for logic circuitry with a small load capacitance; (2) the gate voltage of the driver transistors is boosted to drive the heavily loaded output nodes. Power is supplied to the driver transistors directly from the external supply voltage to avoid stressing the embedded charge pump circuit. GO-CMOS achieves 1/2 gate delay time or 1/15 power dissipation in 0.5V operation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | sub-1V / low Vt / charge pump / low power dissipation |
| Paper # | ED97-47 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Circuit Techniques for 0.5V Single Power Supply Operated Devices |
| Sub Title (in English) | |
| Keyword(1) | sub-1V |
| Keyword(2) | low Vt |
| Keyword(3) | charge pump |
| Keyword(4) | low power dissipation |
| 1st Author's Name | Toru Iwata |
| 1st Author's Affiliation | Corporate Semiconductor Development Division Matsushita Electric Industrial C0.,LTD.() |
| 2nd Author's Name | Yutaka Terada |
| 2nd Author's Affiliation | Corporate Semiconductor Development Division Matsushita Electric Industrial C0.,LTD. |
| 3rd Author's Name | Hironori Akamatsu |
| 3rd Author's Affiliation | Corporate Semiconductor Development Division Matsushita Electric Industrial C0.,LTD. |
| 4th Author's Name | Akira Matsuzawa |
| 4th Author's Affiliation | Corporate Semiconductor Development Division Matsushita Electric Industrial C0.,LTD. |
| 5th Author's Name | Hiroyuki Yamauchi |
| 5th Author's Affiliation | Corporate Semiconductor Development Division Matsushita Electric Industrial C0.,LTD. |
| Date | 1997/6/19 |
| Paper # | ED97-47 |
| Volume (vol) | vol.97 |
| Number (no) | 110 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |