| Presentation | 1997/6/19 A 300 MIPS/W RISC Core Processor with Variable Supply-Voltage Scheme in Variable Threshold-Voltage CMOS Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Tadahiro Kuroda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 300MIPS/W RISC core processor with variable supply-voltage (VS) scheme in variable threshold-voltage CMOS (VTCMOS) is presented. From a 3.3V extemal supply the VS scheme automatically generates minimum internal supply voltages which can meet the demand on its operation frequency. This chip needs only 3.3V power supply, but low-power operation can be achieved by lowering the supply-voltage with on-chip DC-DC converter. Performance in MIPS/W can be improved by a factor of more than two with no modification in the RISC core except substrate contacts for the VICMOS. It is also demonstrated that the VS scheme is immune from supply-voltage fluctuations. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DC-DC converter / VS scheme / variable supply-voltage / low-power / RISC processor / VICMOS |
| Paper # | ED97-46 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 300 MIPS/W RISC Core Processor with Variable Supply-Voltage Scheme in Variable Threshold-Voltage CMOS |
| Sub Title (in English) | |
| Keyword(1) | DC-DC converter |
| Keyword(2) | VS scheme |
| Keyword(3) | variable supply-voltage |
| Keyword(4) | low-power |
| Keyword(5) | RISC processor |
| Keyword(6) | VICMOS |
| 1st Author's Name | Kojiro Suzuki |
| 1st Author's Affiliation | System ULSI Eng. Lab., Toshiba Corp.() |
| 2nd Author's Name | Shinji Mita |
| 2nd Author's Affiliation | System ULSI Eng. Lab., Toshiba Corp. |
| 3rd Author's Name | Tetsuya Fujita |
| 3rd Author's Affiliation | System ULSI Eng. Lab., Toshiba Corp. |
| 4th Author's Name | Fumiyuki Yamane |
| 4th Author's Affiliation | System ULSI Eng. Lab., Toshiba Corp. |
| 5th Author's Name | Fumihiko Sano |
| 5th Author's Affiliation | System LSI Development Division, Toshiba Micro Electronics Corp. |
| 6th Author's Name | Akihiko Chiba |
| 6th Author's Affiliation | System LSI Development Division, Toshiba Micro Electronics Corp. |
| 7th Author's Name | Yoshinori Watanabe |
| 7th Author's Affiliation | System LSI Development Division, Toshiba Micro Electronics Corp. |
| 8th Author's Name | Koji Matsuda |
| 8th Author's Affiliation | System LSI Development Division, Toshiba Micro Electronics Corp. |
| 9th Author's Name | Takeo Maeda |
| 9th Author's Affiliation | Semiconductor Group, Toshiba Corp. |
| 10th Author's Name | Tadahiro Kuroda |
| 10th Author's Affiliation | System ULSI Eng. Lab., Toshiba Corp. |
| Date | 1997/6/19 |
| Paper # | ED97-46 |
| Volume (vol) | vol.97 |
| Number (no) | 110 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |