Presentation 1997/6/19
A Full-Digital PLL for Low Voltage LSIs
Kouichi Ishimi, Katsunori Sawai, Kazuyoshi Shimizu,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A Full-Digital PLL fully integrated with digital CMOS circuits has been developed and was built into 32bit-RISC microprocessor. The oscillation frequency and the phase are adjusted by controlling the delay of digital delay-line with a digital counter. The Input clock frequency is multiplied by 4, and the range of output clock frequency is 20MHz to 120MHz. Measured jitter is 400ps or less, under the power supply voltage between 2.8V and 3.8V, and the ambient temperature between 75℃ and -5℃. It operates within the range of the power supply voltage between 0.6V and 5.3V. It is suitable for the power management function compared with conventional analog PLL.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) PLL / DLL / Low power / Clock generator / Frequency multiplication / Jitter / Power management
Paper # ED97-45
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Conference Date 1997/6/19(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Full-Digital PLL for Low Voltage LSIs
Sub Title (in English)
Keyword(1) PLL
Keyword(2) DLL
Keyword(3) Low power
Keyword(4) Clock generator
Keyword(5) Frequency multiplication
Keyword(6) Jitter
Keyword(7) Power management
1st Author's Name Kouichi Ishimi
1st Author's Affiliation Microcomputer & ASIC Division, Mitsubishi Electric Corp.()
2nd Author's Name Katsunori Sawai
2nd Author's Affiliation Microcomputer & ASIC Division, Mitsubishi Electric Corp.
3rd Author's Name Kazuyoshi Shimizu
3rd Author's Affiliation Microcomputer & ASIC Division, Mitsubishi Electric Corp.
Date 1997/6/19
Paper # ED97-45
Volume (vol) vol.97
Number (no) 110
Page pp.pp.-
#Pages 8
Date of Issue