Presentation 1997/6/19
A2.4-Gb/s CMOS Clock Recovering 1:8 Demultiplexer
M. Soda, A. Tanabe, H. Tezuka, S. Shioiri, M. Togo, T. Tamura, K. Yoshida, A. Furukawa,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 2.4-Gb/s clock recovering 1:8 demultiplexer with extremely low power consumption, has been developed using 0.15μm gate CMOS technology. For higher operation speed, a clock recovering is achieved by a PLL, synchronizing with half the period of input data. A newly designed phase comparator in the PLL compares the phase differences between the data and the half clock. The core circuit of the IC dissipates only 87 mW with 2-V supply voltage.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) optical receiver / PLL / DMUX / CMOS
Paper # ED97-44
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Conference Date 1997/6/19(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A2.4-Gb/s CMOS Clock Recovering 1:8 Demultiplexer
Sub Title (in English)
Keyword(1) optical receiver
Keyword(2) PLL
Keyword(3) DMUX
Keyword(4) CMOS
1st Author's Name M. Soda
1st Author's Affiliation Opto-Electronics Research Labs. NEC Corporation()
2nd Author's Name A. Tanabe
2nd Author's Affiliation Microelectronics Research Labs. NEC Corporation
3rd Author's Name H. Tezuka
3rd Author's Affiliation Opto-Electronics Research Labs. NEC Corporation
4th Author's Name S. Shioiri
4th Author's Affiliation Opto-Electronics Research Labs. NEC Corporation
5th Author's Name M. Togo
5th Author's Affiliation Microelectronics Research Labs. NEC Corporation
6th Author's Name T. Tamura
6th Author's Affiliation ULSI Device Development Labs. NEC Corporation
7th Author's Name K. Yoshida
7th Author's Affiliation ULSI Device Development Labs. NEC Corporation
8th Author's Name A. Furukawa
8th Author's Affiliation Microelectronics Research Labs. NEC Corporation
Date 1997/6/19
Paper # ED97-44
Volume (vol) vol.97
Number (no) 110
Page pp.pp.-
#Pages 6
Date of Issue