| Presentation | 1997/6/19 SOI/CMOS Circuit Design for High-speed Communication LSIs Takanori HIROTA, Kimio UEDA, Yoshiki WADA, Shigenobu MAEDA, Koichiro MASHIKO, Hisanori HAMANO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper compares circuit features between SOI/CMOS and bulk/CMOS devices to realize high-speed communication LSIs. It is required to design circuits with small fan outs and short wires to take advantage of low-power and high-speed SOI/CMOS devices to their fullest. Also, a pass transistor logic is suitable to take the advantages of SOI/CMOS devices. Based on these results, we propose a new flip-flop circuit and a buffer circuit for high-speed communication LSIs. An 8-bit frequency divider and a 4-bit demultiplexer were fabricated using the proposed circuits and 0.35μm process. The 8-bit divider and the 4-bit demultiplexer operated at 2.8GHz and 1.6GHz, respectively, at 2.0V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multiplexer / demultiplexer / CMOS device / SOI/CMOS device / low-power / high-speed |
| Paper # | ED97-43 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | SOI/CMOS Circuit Design for High-speed Communication LSIs |
| Sub Title (in English) | |
| Keyword(1) | multiplexer |
| Keyword(2) | demultiplexer |
| Keyword(3) | CMOS device |
| Keyword(4) | SOI/CMOS device |
| Keyword(5) | low-power |
| Keyword(6) | high-speed |
| 1st Author's Name | Takanori HIROTA |
| 1st Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp.() |
| 2nd Author's Name | Kimio UEDA |
| 2nd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 3rd Author's Name | Yoshiki WADA |
| 3rd Author's Affiliation | ULSI Laboratory, Mitsubishi Electric Corp. |
| 4th Author's Name | Shigenobu MAEDA |
| 4th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 5th Author's Name | Koichiro MASHIKO |
| 5th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| 6th Author's Name | Hisanori HAMANO |
| 6th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corp. |
| Date | 1997/6/19 |
| Paper # | ED97-43 |
| Volume (vol) | vol.97 |
| Number (no) | 110 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |