| Presentation | 1997/6/19 High-performance TSPC DFF R. Kusaba, T. Kondo, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is very important to improve DFF in its area and consumption power because DFF significantly reduces the area and consumption power in VLSIs. The proposed DFF is a semi-static TSPC(True-single-phrase clocking) circuit, which achieves improvement in consumption power, toggle frequency and noise endurance. In spite of unmatched NMOS and PMOS numbers, the DFF is placed in the fewer wiring pitches than the conventional compact one by placing two series of NMOS transistors under 0.25μm process. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DFF / TSPC / Semi-static / Low power / CMOS / LSI |
| Paper # | ED97-42 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-performance TSPC DFF |
| Sub Title (in English) | |
| Keyword(1) | DFF |
| Keyword(2) | TSPC |
| Keyword(3) | Semi-static |
| Keyword(4) | Low power |
| Keyword(5) | CMOS |
| Keyword(6) | LSI |
| 1st Author's Name | R. Kusaba |
| 1st Author's Affiliation | NTT System Electronics Laboratories() |
| 2nd Author's Name | T. Kondo |
| 2nd Author's Affiliation | (Present address)NTT Human Interface Laboratories |
| Date | 1997/6/19 |
| Paper # | ED97-42 |
| Volume (vol) | vol.97 |
| Number (no) | 110 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |