Presentation	1997/6/19 High Speed CPL circuit with booster amplifire for low power operation Takahiro Yamashita, Kunihiro Asada,
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Abstract(in English)	We have studied a new pass transistor logic with sense amplifiers in the middle of the transistor chain to recover signal swing, so that a sense amplifire can detect a small signal voltage faster. Applying the proposed technique to a 16 bit adder, it is demonstrated that the output responds 2.4 times as fast as the conventional CMOS at a supply voltage of 1.5V. Since this circuit requiers multi-phase clocking, we have also studied on the optimum timing of the clocks and a clock generation circuit. We have designed two VLSI chips based on the present method.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	pass transistor / CPL / adder / sense amplifire
Paper #	ED97-41
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Conference Information
Committee	ICD
Conference Date	1997/6/19(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	High Speed CPL circuit with booster amplifire for low power operation
Sub Title (in English)
Keyword(1)	pass transistor
Keyword(2)	CPL
Keyword(3)	adder
Keyword(4)	sense amplifire
1st Author's Name	Takahiro Yamashita
1st Author's Affiliation	Faculty of Engineering, University of Tokyo()
2nd Author's Name	Kunihiro Asada
2nd Author's Affiliation	Faculty of Engineering, University of Tokyo
Date	1997/6/19
Paper #	ED97-41
Volume (vol)	vol.97
Number (no)	110
Page	pp.pp.-
#Pages	8
Date of Issue