| Presentation | 1997/7/25 Searchable Address Queue for ATM switch Masahiko Ishiwaki, Hiromi Notani, Harufusa Kondoh, Hirotaka Saito, Atsushi Iwabu, Kazuo Kawaguchi, Masaya Kitao, Yasunobu Nakase, Yoshio Matsuda, Takeshi Tokuda, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We developed a 622-Mb/s 32 x 8 shared buffering ATM switch chip set with searchable address queue. This chip set consists two LSIs; the Buffer LSI which stores ATM cells to on-chip RAM and the Control LSI which manages the address of the RAM. The key component of this Control LSI is a searchable address queue. This queue has a combination of a double-edge triggered shift register FIFO and a search circuit. These registers are controlled by clocked C elements and store the addresses with destination and delay priority of the ATM cells. Using this queue, the bit size is reduced to 4% as compared with the conventional FIFO and the layout size becomes 5.8mm x 7.8mm. As a result, the address queue can be integrated on one chip. This chip set was fabricated using 0.5-μm CMOS process technology. Inter-stage data shift speed is measured over 571 megastgae/sec at 3.3V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ATM / ATM switch / share buffer / queue |
| Paper # | ICD97-89 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/7/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Searchable Address Queue for ATM switch |
| Sub Title (in English) | |
| Keyword(1) | ATM |
| Keyword(2) | ATM switch |
| Keyword(3) | share buffer |
| Keyword(4) | queue |
| 1st Author's Name | Masahiko Ishiwaki |
| 1st Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Hiromi Notani |
| 2nd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 3rd Author's Name | Harufusa Kondoh |
| 3rd Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 4th Author's Name | Hirotaka Saito |
| 4th Author's Affiliation | Information & Communication System Development Center, Mitsubishi Electric Corppration |
| 5th Author's Name | Atsushi Iwabu |
| 5th Author's Affiliation | LSI Engineering Office, Mitsubishi Electric Eng. Co., Ltd. |
| 6th Author's Name | Kazuo Kawaguchi |
| 6th Author's Affiliation | LSI Engineering Office, Mitsubishi Electric Eng. Co., Ltd. |
| 7th Author's Name | Masaya Kitao |
| 7th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 8th Author's Name | Yasunobu Nakase |
| 8th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 9th Author's Name | Yoshio Matsuda |
| 9th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| 10th Author's Name | Takeshi Tokuda |
| 10th Author's Affiliation | System LSI Laboratory, Mitsubishi Electric Corporation |
| Date | 1997/7/25 |
| Paper # | ICD97-89 |
| Volume (vol) | vol.97 |
| Number (no) | 198 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |