Presentation	1997/5/22 Two-port Cache Macro for Low-Power RISC Processor Ken-Ich Osada, Hisayuki Higuchi, Koichiro Ishibashi, Naotaka Hashimoto, Kenji Shiozawa,
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Abstract(in English)	Two-port 16-KB (512x256b) cache is fabricated using 0.35 μm 4-metal CMOS technology. This cache operates at 285MHz and has 2-ns access time. This performance is achieved through a hierarchical bit line architecture which uses double global bit line pairs (WGB). A timing-free sense amplifier is also proposed to achieve the short access time.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Microprocessor / RISC / Cache / SRAM / 2-port
Paper #	ICD97-22
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Conference Information
Committee	ICD
Conference Date	1997/5/22(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Two-port Cache Macro for Low-Power RISC Processor
Sub Title (in English)
Keyword(1)	Microprocessor
Keyword(2)	RISC
Keyword(3)	Cache
Keyword(4)	SRAM
Keyword(5)	2-port
1st Author's Name	Ken-Ich Osada
1st Author's Affiliation	Central Research Laboratory, Hitachi, Ltd.()
2nd Author's Name	Hisayuki Higuchi
2nd Author's Affiliation	Central Research Laboratory, Hitachi, Ltd.
3rd Author's Name	Koichiro Ishibashi
3rd Author's Affiliation	Central Research Laboratory, Hitachi, Ltd.
4th Author's Name	Naotaka Hashimoto
4th Author's Affiliation	Semiconductor & Integrated Circuits Division, Hitachi Ltd.
5th Author's Name	Kenji Shiozawa
5th Author's Affiliation	Semiconductor & Integrated Circuits Division, Hitachi Ltd.
Date	1997/5/22
Paper #	ICD97-22
Volume (vol)	vol.97
Number (no)	56
Page	pp.pp.-
#Pages	6
Date of Issue