| Presentation | 1997/5/22 A sensing scheme for a ACT flash memory Y. Hirano, Y. Ohta, S. Tanno, K. Yamamoto, S. Endo, K. Nakahara, T. Mimoto, H. Shimizu, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The boost type sensing scheme and the new block erase verify method for the ACT type flash memory using a virtual ground array are proposed in order to decrease the erase and program verify time. The boost type sensing and the new block erase verify operation are confirmed by using circuit simulations. The simulation results have shown that the discharge time is decreased by this method in compared with the conventional sensing scheme. The erase verify time and power consumption are improved by using the new block erase verify method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | EEPROM / Flash memory / Sense amplifier / Virtual ground / Erase verify / High speed access |
| Paper # | ICD97-21 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/5/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A sensing scheme for a ACT flash memory |
| Sub Title (in English) | |
| Keyword(1) | EEPROM |
| Keyword(2) | Flash memory |
| Keyword(3) | Sense amplifier |
| Keyword(4) | Virtual ground |
| Keyword(5) | Erase verify |
| Keyword(6) | High speed access |
| 1st Author's Name | Y. Hirano |
| 1st Author's Affiliation | Flash Memory Engineering Dept. I, Tenri IC Development Group, SHARP Corporation() |
| 2nd Author's Name | Y. Ohta |
| 2nd Author's Affiliation | Flash Memory Engineering Dept. I, Tenri IC Development Group, SHARP Corporation |
| 3rd Author's Name | S. Tanno |
| 3rd Author's Affiliation | Flash Memory Engineering Dept. I, Tenri IC Development Group, SHARP Corporation |
| 4th Author's Name | K. Yamamoto |
| 4th Author's Affiliation | Flash Memory Engineering Dept. I, Tenri IC Development Group, SHARP Corporation |
| 5th Author's Name | S. Endo |
| 5th Author's Affiliation | Flash Memory Engineering Dept. I, Tenri IC Development Group, SHARP Corporation |
| 6th Author's Name | K. Nakahara |
| 6th Author's Affiliation | Flash Memory Engineering Dept. I, Tenri IC Development Group, SHARP Corporation |
| 7th Author's Name | T. Mimoto |
| 7th Author's Affiliation | Flash Memory Engineering Dept. I, Tenri IC Development Group, SHARP Corporation |
| 8th Author's Name | H. Shimizu |
| 8th Author's Affiliation | VLSI Research Laboratory, Tenri IC Development Group, SHARP Corporation |
| Date | 1997/5/22 |
| Paper # | ICD97-21 |
| Volume (vol) | vol.97 |
| Number (no) | 56 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |