| Presentation | 1997/5/22 A 256Mb SDRAM Using a Register-Controlled Digital DLL Tadao Aikawa, Hirohiko Mochizuki, Atsusi Hatakeyama, Masato Takita, Shinya Fujioka, Shusaku Yamaguchi, Koichi Nishimura, Yoshinori Okajima, Michiari Kawano, Hideyuki Kojima, Kazuhiro Mizutani, Masao Taguchi, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Currently, significant improvements in operating speed of DRAMs are strongly required. It is, thereby, essential to attain maximized data-valid time window for each I/O port while making clock frequencies higher. For this purpose, we developed a 256-Mb synchronous DRAM using a new circuit technique named RDLL (Register Controlled DLL). The resultant clock access time was measured 1ns on our experimental chip. In our design, sense amplifiers have been optimized for low voltage operation through improving transistor biasing scheme and the layout pattern, to expand the supply voltage margin. An innovative memory cell structure, SBC cell was developed using the self-aligned contact technology to make process steps the minimum and moderate lithographic difficulty. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 256MSDRAM / clock synchronization / DLL / sense amplifier / cylindrical capacitor cell |
| Paper # | ICD97-18 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 1997/5/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 256Mb SDRAM Using a Register-Controlled Digital DLL |
| Sub Title (in English) | |
| Keyword(1) | 256MSDRAM |
| Keyword(2) | clock synchronization |
| Keyword(3) | DLL |
| Keyword(4) | sense amplifier |
| Keyword(5) | cylindrical capacitor cell |
| 1st Author's Name | Tadao Aikawa |
| 1st Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited() |
| 2nd Author's Name | Hirohiko Mochizuki |
| 2nd Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 3rd Author's Name | Atsusi Hatakeyama |
| 3rd Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 4th Author's Name | Masato Takita |
| 4th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 5th Author's Name | Shinya Fujioka |
| 5th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 6th Author's Name | Shusaku Yamaguchi |
| 6th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 7th Author's Name | Koichi Nishimura |
| 7th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 8th Author's Name | Yoshinori Okajima |
| 8th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 9th Author's Name | Michiari Kawano |
| 9th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 10th Author's Name | Hideyuki Kojima |
| 10th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 11th Author's Name | Kazuhiro Mizutani |
| 11th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| 12th Author's Name | Masao Taguchi |
| 12th Author's Affiliation | DRAM Division, LSI Products Group, Fujitsu Limited |
| Date | 1997/5/22 |
| Paper # | ICD97-18 |
| Volume (vol) | vol.97 |
| Number (no) | 56 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |