| Presentation | 1997/5/22 On-Wafer BIST of a 200Gb/s Failed-Bit Search for 1Gb DRAM Atsuhiko Okada, Satoru Tanoi, Yasuhiro Tokunaga, Tetsuya Tnabe, Kazuhiko Takahashi, Masahiro Itoh, Yoshiki Nagatomo, Yoshio Ohtsuki, Masaru Uesugi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 200Gb/s failed-bit searchable 1Gb DRAM has been developed using an on-wafer BIST technique. Included circuits are a 4kb very-long word bus to probe the array circuits and on-wafer test management units to compress the test results. This BIST shortens a wafer test time to less than 1/100 compared with bit-by-bit testing. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DRAM / BIST / test / giga-bit / very-long-word / search |
| Paper # | ICD97-17 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/5/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On-Wafer BIST of a 200Gb/s Failed-Bit Search for 1Gb DRAM |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | BIST |
| Keyword(3) | test |
| Keyword(4) | giga-bit |
| Keyword(5) | very-long-word |
| Keyword(6) | search |
| 1st Author's Name | Atsuhiko Okada |
| 1st Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd.() |
| 2nd Author's Name | Satoru Tanoi |
| 2nd Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd. |
| 3rd Author's Name | Yasuhiro Tokunaga |
| 3rd Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd. |
| 4th Author's Name | Tetsuya Tnabe |
| 4th Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd. |
| 5th Author's Name | Kazuhiko Takahashi |
| 5th Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd. |
| 6th Author's Name | Masahiro Itoh |
| 6th Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd. |
| 7th Author's Name | Yoshiki Nagatomo |
| 7th Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd. |
| 8th Author's Name | Yoshio Ohtsuki |
| 8th Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd. |
| 9th Author's Name | Masaru Uesugi |
| 9th Author's Affiliation | VLSI R & D Center Oki Electric Industry Co., Ltd. |
| Date | 1997/5/22 |
| Paper # | ICD97-17 |
| Volume (vol) | vol.97 |
| Number (no) | 56 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |