Presentation	1997/4/24 Partitioned and Pipelined Bus Architecture in VLSI Makoto IKEDA, Yoshitake TAJIMA, Kunihiro ASADA,
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Abstract(in English)	This paper describes a pipelined-bus architecture to enhance through-put of bus lines in the advanced VLSIs. We have also studied the optimum bus architecture for design rules in terms of bus wiring delay and wiring area, and found that the conventional bus architecture is the optimum for a 0.5μm rule, and that a bus with repeater is the optimum for a 0.35μm rule, and that the pipelined-bus architecture is the optimum for a 0.2μm rule and below.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Pipelined-bus / repeated-bus / microprocessor / wiring delay / bus wiring area / multi-layer wiring
Paper #	ICD97-4,CPSY97-4,FTS97-4
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Conference Information
Committee	ICD
Conference Date	1997/4/24(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Partitioned and Pipelined Bus Architecture in VLSI
Sub Title (in English)
Keyword(1)	Pipelined-bus
Keyword(2)	repeated-bus
Keyword(3)	microprocessor
Keyword(4)	wiring delay
Keyword(5)	bus wiring area
Keyword(6)	multi-layer wiring
1st Author's Name	Makoto IKEDA
1st Author's Affiliation	VLSI Design and Education Center, University of Tokyo()
2nd Author's Name	Yoshitake TAJIMA
2nd Author's Affiliation	VLSI Design and Education Center, University of Tokyo
3rd Author's Name	Kunihiro ASADA
3rd Author's Affiliation	VLSI Design and Education Center, University of Tokyo
Date	1997/4/24
Paper #	ICD97-4,CPSY97-4,FTS97-4
Volume (vol)	vol.97
Number (no)	24
Page	pp.pp.-
#Pages	8
Date of Issue