Presentation 1997/4/24
A Compact 54x54b Multiplier Utilizing Sign Select Booth Encoders
Shoichiro Kashiwakura, Atsuki Inoue, Ryoichi Ohe, Shin Mitarai, Takayuki Tsuru, Tetsuo Izawa, Gensuke Goto,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 54x54b multiplier with 4.1ns latency at 2.5V supply and a 1.27mm^2 active area was implemented on 0.25μm CMOS with 5.5nm gate oxide and Co salicidation process. Utilizing sign select Booth encoder, the total transistor count is reduced by 24% from the conventional multiplier and the world's smallest multiplier is achieved.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Multiplier / Booth algorithm / compact / 0.25μm CMOS / 2.5V supply
Paper # ICD97-3,CPSY97-3,FTS97-3
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Committee ICD
Conference Date 1997/4/24(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Compact 54x54b Multiplier Utilizing Sign Select Booth Encoders
Sub Title (in English)
Keyword(1) Multiplier
Keyword(2) Booth algorithm
Keyword(3) compact
Keyword(4) 0.25μm CMOS
Keyword(5) 2.5V supply
1st Author's Name Shoichiro Kashiwakura
1st Author's Affiliation FUJITSU LABORATORIES LIMITED()
2nd Author's Name Atsuki Inoue
2nd Author's Affiliation FUJITSU LABORATORIES LIMITED
3rd Author's Name Ryoichi Ohe
3rd Author's Affiliation FUJITSU LABORATORIES LIMITED
4th Author's Name Shin Mitarai
4th Author's Affiliation FUJITSU LIMITED
5th Author's Name Takayuki Tsuru
5th Author's Affiliation FUJITSU LIMITED
6th Author's Name Tetsuo Izawa
6th Author's Affiliation FUJITSU LIMITED
7th Author's Name Gensuke Goto
7th Author's Affiliation FUJITSU LABORATORIES LIMITED
Date 1997/4/24
Paper # ICD97-3,CPSY97-3,FTS97-3
Volume (vol) vol.97
Number (no) 24
Page pp.pp.-
#Pages 8
Date of Issue