| Presentation | 1997/4/24 Performance comparison of asynchronous adders considering wire delays Masashi Imai, Takashi Nanya, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An asynchronous circuit is an event-driven logic, which first acknowledges the completion of an event before starting the next one. The circuit performance is evaluated by its average delay In order to study the performance of the asynchronous versions of synchronous adders that have already been presented in the literature, we designed 32-bit asynchronous adders which were integrated on a single chip In this paper, we first present the structure of the chip which includes 4 kinds of adder circuits and extra circuits for evaluation on purpose Then, we show the simulation results of delay evaluation Next, we show the results obtained by the evaluation chip, and show the most suitable adder design for asynchronous circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | asynchronous circuit / adder design / average delay / wire delay |
| Paper # | ICD97-2,CPSY97-2,FTS97-2 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/4/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance comparison of asynchronous adders considering wire delays |
| Sub Title (in English) | |
| Keyword(1) | asynchronous circuit |
| Keyword(2) | adder design |
| Keyword(3) | average delay |
| Keyword(4) | wire delay |
| 1st Author's Name | Masashi Imai |
| 1st Author's Affiliation | Research Center for Advanced Science and Technology, University of Tokyo() |
| 2nd Author's Name | Takashi Nanya |
| 2nd Author's Affiliation | Research Center for Advanced Science and Technology, University of Tokyo |
| Date | 1997/4/24 |
| Paper # | ICD97-2,CPSY97-2,FTS97-2 |
| Volume (vol) | vol.97 |
| Number (no) | 24 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |