| Presentation | 1997/4/24 A 1GHz 64bit ALU Datapath using Variable Latency Pipeline Structure Kiyoji Ueno, Nobuyuki Ikumi, Yoshihisa Kondo, Junji Mori, Masashi Hirano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A Variable Latency Pipelining design techniques is proposed. By using the design technique, a 1GHz ALU datapath including a register file and bypass circuits has been implemented in 0.25μm CMOS 5-layer wiring technology. The technique has reduced cycle time from 1.5ns to 1ns and improved performance by about 33%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Variable Latency Pipeline / Microprocessor / ALU / Datapath / CMOS |
| Paper # | ICD97-1,CPSY97-1,FTS97-1 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 1997/4/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 1GHz 64bit ALU Datapath using Variable Latency Pipeline Structure |
| Sub Title (in English) | |
| Keyword(1) | Variable Latency Pipeline |
| Keyword(2) | Microprocessor |
| Keyword(3) | ALU |
| Keyword(4) | Datapath |
| Keyword(5) | CMOS |
| 1st Author's Name | Kiyoji Ueno |
| 1st Author's Affiliation | Toshiba Microelectronics Engineering Laboratory() |
| 2nd Author's Name | Nobuyuki Ikumi |
| 2nd Author's Affiliation | Toshiba Microelectronics Engineering Laboratory |
| 3rd Author's Name | Yoshihisa Kondo |
| 3rd Author's Affiliation | Toshiba Microelectronics Engineering Laboratory |
| 4th Author's Name | Junji Mori |
| 4th Author's Affiliation | Toshiba Microelectronics Engineering Laboratory |
| 5th Author's Name | Masashi Hirano |
| 5th Author's Affiliation | Toshiba Microelectronics Engineering Laboratory |
| Date | 1997/4/24 |
| Paper # | ICD97-1,CPSY97-1,FTS97-1 |
| Volume (vol) | vol.97 |
| Number (no) | 24 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |