| Presentation | 2001/9/20 Development of Physical Design Technology at STARC: Target and Activities Hiroo MASUDA, Hiroyuki HARA, Fumihiro MINAMI, Atsushi MARUYAMA, Shinichi FUJIMOTO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Highly functional and high-performance SoC becomes practical target with scaled CMOS process available. However, classical physical mechanism, enhanced by small dimension process, becomes increasingly critical issues in terms of Signal Integrity (SI) design. On-chip interconnect L (inductance) under high frequency operation, crosstalk and IR drop on power grids, all of these physical design can be bottle-neck in a practical SoC development. STARC attacks this design problems with Test Structure fabricated updated process and intensive experiments on the SI phenomena. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SoC(System on a Chip) / SI(Signal Integrity) / TEG(Test Element Group) / STARC / Physical Design |
| Paper # | VLD2001-72,SDM2001-146 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2001/9/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Physical Design Technology at STARC: Target and Activities |
| Sub Title (in English) | |
| Keyword(1) | SoC(System on a Chip) |
| Keyword(2) | SI(Signal Integrity) |
| Keyword(3) | TEG(Test Element Group) |
| Keyword(4) | STARC |
| Keyword(5) | Physical Design |
| 1st Author's Name | Hiroo MASUDA |
| 1st Author's Affiliation | Semiconductor Technology Academic Research Center (STARC)() |
| 2nd Author's Name | Hiroyuki HARA |
| 2nd Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 3rd Author's Name | Fumihiro MINAMI |
| 3rd Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 4th Author's Name | Atsushi MARUYAMA |
| 4th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| 5th Author's Name | Shinichi FUJIMOTO |
| 5th Author's Affiliation | Semiconductor Technology Academic Research Center (STARC) |
| Date | 2001/9/20 |
| Paper # | VLD2001-72,SDM2001-146 |
| Volume (vol) | vol.101 |
| Number (no) | 320 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |