Presentation | 2001/9/20 A Simple simulation Technique for Analyzing of Substrate Coupling Tomohisa KIMURA, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A simple simulation technique for analyzing substrate coupling effect is proposed. In this method, a substrate network model is extracted from the layout data. Test chips were fabricated and measured for demonstrating the effectiveness of the proposed technique. Simulated results were compared with the measured results. This comparison shows the validity of the simulation method. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Substrate Coupling / Circuit Simulation / Isolation / Layout CAD / Modeling / Extraction |
Paper # | VLD2001-69,SDM2001-143 |
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Conference Information | |
Committee | SDM |
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Conference Date | 2001/9/20(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Silicon Device and Materials (SDM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Simple simulation Technique for Analyzing of Substrate Coupling |
Sub Title (in English) | |
Keyword(1) | Substrate Coupling |
Keyword(2) | Circuit Simulation |
Keyword(3) | Isolation |
Keyword(4) | Layout CAD |
Keyword(5) | Modeling |
Keyword(6) | Extraction |
1st Author's Name | Tomohisa KIMURA |
1st Author's Affiliation | Toshiba R&D Center() |
Date | 2001/9/20 |
Paper # | VLD2001-69,SDM2001-143 |
Volume (vol) | vol.101 |
Number (no) | 320 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |