Presentation 2001/6/28
A Thorough Study of Thin Gate Oxide Degradation during Fabrication of Advanced CMOSFET's
Jae-Sung Lee, Heui-Gyun Ahn, Won-Gyu Lee,
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Abstract(in English) This study is focused on the analytical method to analyze the degradation of gate oxide integrity. The current components of p-MOSFET's were measured with carrier separation method. For comprehensive understanding, we used three kinds of devices, which are the fresh, the stressed, and the damaged devices. With the information for composition of gate current, the location of the damage layer in gate oxide can be deduced. In our device, valence hole tunneling current is the dominant component of gate current in inversion mode, which implies the damage region was generated near polysilicon/SiO_2 interface.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Gate oxide degradation / carrier separation method / valence hole tunneling current
Paper # ED2001-63,SDM2001-70
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Committee SDM
Conference Date 2001/6/28(1days)
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Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Thorough Study of Thin Gate Oxide Degradation during Fabrication of Advanced CMOSFET's
Sub Title (in English)
Keyword(1) Gate oxide degradation
Keyword(2) carrier separation method
Keyword(3) valence hole tunneling current
1st Author's Name Jae-Sung Lee
1st Author's Affiliation Dept.of Computer & Communication Eng.Uiduk University()
2nd Author's Name Heui-Gyun Ahn
2nd Author's Affiliation System IC R&D Lab.
3rd Author's Name Won-Gyu Lee
3rd Author's Affiliation System IC R&D Lab.
Date 2001/6/28
Paper # ED2001-63,SDM2001-70
Volume (vol) vol.101
Number (no) 163
Page pp.pp.-
#Pages 5
Date of Issue