| Presentation | 2001/5/18 Estimation of structure simulation in order to control the short channel effect in NMOSFET Tadaoki Yamamoto, Keigo Nakasima, Kazuyuki Sibata, Hideo Uchida, Masaya Ichimura, Eisuke Arai, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We tried to obtain the device parameters to control the short channel effect for MOSFETs with the elevated source/drain structure and counter doping structure using device simulator. For the elevated structure, the decrease of drain current is observed but is improved by adding the halo structure. For the counter doping structure, we can control the short channel effect for any threshold voltage. For reduction of device dimension in future, the counter doping structure is superior to the elevated one since it has the wide control range of threshold voltage. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | elevated source and drain / counter doping / short channel effect / simulation / halo structure |
| Paper # | ED2001-40,CPM2001-27,SDM2001-40 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2001/5/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Estimation of structure simulation in order to control the short channel effect in NMOSFET |
| Sub Title (in English) | |
| Keyword(1) | elevated source and drain |
| Keyword(2) | counter doping |
| Keyword(3) | short channel effect |
| Keyword(4) | simulation |
| Keyword(5) | halo structure |
| 1st Author's Name | Tadaoki Yamamoto |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology() |
| 2nd Author's Name | Keigo Nakasima |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 3rd Author's Name | Kazuyuki Sibata |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 4th Author's Name | Hideo Uchida |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 5th Author's Name | Masaya Ichimura |
| 5th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 6th Author's Name | Eisuke Arai |
| 6th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| Date | 2001/5/18 |
| Paper # | ED2001-40,CPM2001-27,SDM2001-40 |
| Volume (vol) | vol.101 |
| Number (no) | 83 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |