| Presentation | 2001/5/18 Evaluation of MOS process under the environment without clean room by utilizing TEG Ryouichi Tomida, Atsushi Tsurumaru, Yasuhiro Kawauti, Takahiro Ikeno, Hideo Uchida, Masaya Ichimura, Eisuke Arai, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | MOS transistors were fabricated under the environment without clean room. TEG (Test Element Group) was used to analyze each part of transistor, i.e., MOS gate,PNjunction and contacts. We used scotch-tape-test to evaluate adhesion between resist and organic-spin-on-glass used as intermediate layer and established contact-hole formation process. We evaluated contact resistivity and examined reduction methods of contact resitivity. After evaluating defect densities of PNjunctions of source and drain, contacts and MOS diodes, we estimated the scale of integration of nMOS IC which can be made in the environment. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | TEG / spin-on-glass / adhesion / contact resistivity / defect density |
| Paper # | ED2001-35,CPN2001-22,SDM2001-35 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
|---|---|
| Conference Date | 2001/5/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of MOS process under the environment without clean room by utilizing TEG |
| Sub Title (in English) | |
| Keyword(1) | TEG |
| Keyword(2) | spin-on-glass |
| Keyword(3) | adhesion |
| Keyword(4) | contact resistivity |
| Keyword(5) | defect density |
| 1st Author's Name | Ryouichi Tomida |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology() |
| 2nd Author's Name | Atsushi Tsurumaru |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 3rd Author's Name | Yasuhiro Kawauti |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 4th Author's Name | Takahiro Ikeno |
| 4th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 5th Author's Name | Hideo Uchida |
| 5th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 6th Author's Name | Masaya Ichimura |
| 6th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| 7th Author's Name | Eisuke Arai |
| 7th Author's Affiliation | Department of Electrical and Computer Engineering, Nagoya Institute of Technology |
| Date | 2001/5/18 |
| Paper # | ED2001-35,CPN2001-22,SDM2001-35 |
| Volume (vol) | vol.101 |
| Number (no) | 83 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |