| Presentation | 2001/3/5 Preparation and Characterization of MIS and MFIS Structures Using MgO Buffer I-Layer Hironori Fujisawa, Shuhei Murata, Hiromasu Matsuoka, Tatsuya Bandou, Masaru Shimizu, Hirohiko Niu, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Metal-insulator-semiconductor (MIS) and metal-ferroelectrics-insulator-semiconductor (MFIS) structures were fabricated using sputtered-MgO thin films as an insulative layer and their electrical properties were investigated. Capacitance-voltage (C-V) characteristics of MIS structure did not show a hysteresis. Interface trap densities of the MIS structure measured using the deep level transient spectroscopy (DLTS) method was approximately 10^<12>eV^<-1>. Crystalline Pb(Zr,Ti)O_3 (PZT) thin films were successfully grown on MgO/Si(100) by metalorganic chemical vapor deposition (MOCVD). Memory windows of 0.2-0.7V due to ferroelectricity of PZT thin films were observed for the MFIS structures. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MgO / Pb(Zr,Ti)O_3 / MFIS / DLTS / interface trap |
| Paper # | SDM2000-233 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2001/3/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Preparation and Characterization of MIS and MFIS Structures Using MgO Buffer I-Layer |
| Sub Title (in English) | |
| Keyword(1) | MgO |
| Keyword(2) | Pb(Zr,Ti)O_3 |
| Keyword(3) | MFIS |
| Keyword(4) | DLTS |
| Keyword(5) | interface trap |
| 1st Author's Name | Hironori Fujisawa |
| 1st Author's Affiliation | Department of Electronics, Faculty of Engineering, Himeji Institute of Technology() |
| 2nd Author's Name | Shuhei Murata |
| 2nd Author's Affiliation | Department of Electronics, Faculty of Engineering, Himeji Institute of Technology |
| 3rd Author's Name | Hiromasu Matsuoka |
| 3rd Author's Affiliation | Department of Electronics, Faculty of Engineering, Himeji Institute of Technology |
| 4th Author's Name | Tatsuya Bandou |
| 4th Author's Affiliation | Department of Electronics, Faculty of Engineering, Himeji Institute of Technology |
| 5th Author's Name | Masaru Shimizu |
| 5th Author's Affiliation | Department of Electronics, Faculty of Engineering, Himeji Institute of Technology |
| 6th Author's Name | Hirohiko Niu |
| 6th Author's Affiliation | Department of Electronics, Faculty of Engineering, Himeji Institute of Technology |
| Date | 2001/3/5 |
| Paper # | SDM2000-233 |
| Volume (vol) | vol.100 |
| Number (no) | 652 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |