| Presentation | 2000/8/18 ED2000-138 / SDM2000-120 / ICD2000-74 Damascene Metal Gate Transistor Technology : Reduction of threshold voltage deviation and salicide integration to damascene gate process Tomohiro SAITO, Atsushi YAGISHITA, Kazuaki NAKAJIMA, Seiji INUMIYA, Koji MATSUO, Toshihiko IINUMA, Atsushi MURAKOSHI, Yasushi AKASAKA, Yoshio OZAWA, Gaku MINAMIHABA, Yukiteru MATSUI, Seiichi OMOTO, Hiroyuki YANO, Katsuhiko HIEDA, Yoshitaka TSUNASHIMA, Kyoichi SUGURO, Tsunetoshi ARIKADO, Katsuya OKUMURA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We proposed the Damascene gate process in order to apply metal gate materials and high-k gate dielectrics to 0.1um node high performance transistors. However, the deviation of crystal orientation of TiN barrier metals was found to affect threshold voltages of the Damascene gate MOSFETs. Therefore, we developed an inorganic CVD technique in order to control the crystal orientation of TiN film. By using this technique, threshold voltage deviation and transconductance were drastically improved. On the other hand, Co salicide films on source/drain are required to be thermally stable because high temperature process is performed after salicide formation in the Damascene gate process. The Damacene metal gate MOSFETs with Co silicided source/drain were successfully formed because the agglomeration of CoSi2 films was reduced by ion implantation through salicide technique. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Damascene gate / threshold voltage deviation / inorganic CVD / Co salicide / agglomeration |
| Paper # | ED2000-138,SDM2000-120,ICD2000-74 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2000/8/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | ED2000-138 / SDM2000-120 / ICD2000-74 Damascene Metal Gate Transistor Technology : Reduction of threshold voltage deviation and salicide integration to damascene gate process |
| Sub Title (in English) | |
| Keyword(1) | Damascene gate |
| Keyword(2) | threshold voltage deviation |
| Keyword(3) | inorganic CVD |
| Keyword(4) | Co salicide |
| Keyword(5) | agglomeration |
| 1st Author's Name | Tomohiro SAITO |
| 1st Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation() |
| 2nd Author's Name | Atsushi YAGISHITA |
| 2nd Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 3rd Author's Name | Kazuaki NAKAJIMA |
| 3rd Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 4th Author's Name | Seiji INUMIYA |
| 4th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 5th Author's Name | Koji MATSUO |
| 5th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 6th Author's Name | Toshihiko IINUMA |
| 6th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 7th Author's Name | Atsushi MURAKOSHI |
| 7th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 8th Author's Name | Yasushi AKASAKA |
| 8th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 9th Author's Name | Yoshio OZAWA |
| 9th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 10th Author's Name | Gaku MINAMIHABA |
| 10th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 11th Author's Name | Yukiteru MATSUI |
| 11th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 12th Author's Name | Seiichi OMOTO |
| 12th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 13th Author's Name | Hiroyuki YANO |
| 13th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 14th Author's Name | Katsuhiko HIEDA |
| 14th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 15th Author's Name | Yoshitaka TSUNASHIMA |
| 15th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 16th Author's Name | Kyoichi SUGURO |
| 16th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 17th Author's Name | Tsunetoshi ARIKADO |
| 17th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| 18th Author's Name | Katsuya OKUMURA |
| 18th Author's Affiliation | Process and Manufacturing Engineering Center., Semiconductor Company, TOSHIBA Corporation |
| Date | 2000/8/18 |
| Paper # | ED2000-138,SDM2000-120,ICD2000-74 |
| Volume (vol) | vol.100 |
| Number (no) | 268 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |