Presentation 2000/8/18
ED2000-128 / SDM2000-110 / ICD2000-64 3.5 Gbps CMOS/SIMOX Transceiver with Limiting Amplifier
Mika Nishisaka, Kazuyoshi Nishimura, Yusuke Ohtomo,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A half-rate PLL circuit and a SOI depletion-layer guard ring were developed to reduce cross-talk noise from digital circuits to analog circuits via substrate. This provides total integration of optical transceiver functions: multiplexer/demultiplexer, PLL, CDR, 8B/10B encoder/decoder, word aligner with limiting amplifier and laser driver. One-chip transceiver fabricated with 0.2μm CMOS/SIMOX process showed 3.3x speed of 3.5 Gb/s with a conventional one and low-power consumption of 450 mW at 2.0Gb/s operation.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Optical transceiver / half-rate circuit / noise guard ring / CMOS/SOI / Low power
Paper # ED2000-128,SDM2000-110,ICD2000-64
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Conference Information
Committee SDM
Conference Date 2000/8/18(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) ED2000-128 / SDM2000-110 / ICD2000-64 3.5 Gbps CMOS/SIMOX Transceiver with Limiting Amplifier
Sub Title (in English)
Keyword(1) Optical transceiver
Keyword(2) half-rate circuit
Keyword(3) noise guard ring
Keyword(4) CMOS/SOI
Keyword(5) Low power
1st Author's Name Mika Nishisaka
1st Author's Affiliation NTT Telecommunications Energy Laboratories()
2nd Author's Name Kazuyoshi Nishimura
2nd Author's Affiliation NTT Telecommunications Energy Laboratories
3rd Author's Name Yusuke Ohtomo
3rd Author's Affiliation NTT Telecommunications Energy Laboratories
Date 2000/8/18
Paper # ED2000-128,SDM2000-110,ICD2000-64
Volume (vol) vol.100
Number (no) 268
Page pp.pp.-
#Pages 6
Date of Issue