Presentation 2000/8/17
ED2000-117 / SDM2000-99 / ICD2000-53 A 450MHz 64bit RISC Processor using Multiple Threshold Voltage CMOS
Takeo Yamashita, Naoki Yoshida, Masatoshi Sakamoto, Takashi Matsumoto, Mitsugu Kusunoki, Hideyuki Takahashi, Atsushi Wakahara, Takuji Ito, Teruhisa Shimizu, Kozaburo Kurita, Keiichi Higeta, Kazutaka Mori, Nobuo Tamba, Naoki Kato, Kazuhisa Miyamoto, Ryo Yamagata, Hirotoshi Tanaka, Toru Hiyama,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 450MHz 64bit RISC processor developed for the Super Technical Server is presented in this paper. The die of 18.5x18.5mm2 contains 8.3million transistors of logic gates and 20million transistors of RAM's. A 0.25mm CMOS of Lg=0.2mm, Tox=4nm, Vdd=1.8V with 7-layer metal technology enables this integration. To achieve this high operation frequency, multiple threshold voltage design is newly introduced with minimum standby current. We have successfully applied it to not only static circuits but also clock distribution drivers, register files and even dynamic circuits in RAM macros to take full advantage of this technique.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Multiple Threshold Voltage / RISC Processor / Substrate Bias / Leak Current / CMOS
Paper # ED2000-117,SDM2000-99,ICD2000-53
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Committee SDM
Conference Date 2000/8/17(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) ED2000-117 / SDM2000-99 / ICD2000-53 A 450MHz 64bit RISC Processor using Multiple Threshold Voltage CMOS
Sub Title (in English)
Keyword(1) Multiple Threshold Voltage
Keyword(2) RISC Processor
Keyword(3) Substrate Bias
Keyword(4) Leak Current
Keyword(5) CMOS
1st Author's Name Takeo Yamashita
1st Author's Affiliation Device Development Center, Hitachi Ltd.()
2nd Author's Name Naoki Yoshida
2nd Author's Affiliation Hitachi ULSI Systems, Co., Ltd.
3rd Author's Name Masatoshi Sakamoto
3rd Author's Affiliation Device Development Center, Hitachi Ltd.
4th Author's Name Takashi Matsumoto
4th Author's Affiliation Device Development Center, Hitachi Ltd.
5th Author's Name Mitsugu Kusunoki
5th Author's Affiliation Device Development Center, Hitachi Ltd.
6th Author's Name Hideyuki Takahashi
6th Author's Affiliation Device Development Center, Hitachi Ltd.
7th Author's Name Atsushi Wakahara
7th Author's Affiliation Device Development Center, Hitachi Ltd.
8th Author's Name Takuji Ito
8th Author's Affiliation Device Development Center, Hitachi Ltd.
9th Author's Name Teruhisa Shimizu
9th Author's Affiliation Device Development Center, Hitachi Ltd.
10th Author's Name Kozaburo Kurita
10th Author's Affiliation Device Development Center, Hitachi Ltd.
11th Author's Name Keiichi Higeta
11th Author's Affiliation Device Development Center, Hitachi Ltd.
12th Author's Name Kazutaka Mori
12th Author's Affiliation Device Development Center, Hitachi Ltd.
13th Author's Name Nobuo Tamba
13th Author's Affiliation Device Development Center, Hitachi Ltd.
14th Author's Name Naoki Kato
14th Author's Affiliation Central Research Laboratory, Hitachi Ltd.
15th Author's Name Kazuhisa Miyamoto
15th Author's Affiliation Enterprise Server Division, Hitachi Ltd.
16th Author's Name Ryo Yamagata
16th Author's Affiliation Enterprise Server Division, Hitachi Ltd.
17th Author's Name Hirotoshi Tanaka
17th Author's Affiliation Enterprise Server Division, Hitachi Ltd.
18th Author's Name Toru Hiyama
18th Author's Affiliation Enterprise Server Division, Hitachi Ltd.
Date 2000/8/17
Paper # ED2000-117,SDM2000-99,ICD2000-53
Volume (vol) vol.100
Number (no) 267
Page pp.pp.-
#Pages 7
Date of Issue