講演名 | 2000/6/21 ED2000-46 / SDM2000-46 Analysis of a High Performance Self-Aligned Elevated Source Drain MOSFET with Reduced Gate-Induced Drain-Leakage , |
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抄録(和) | |
抄録(英) | A novel self-aligned ESD (Elevated Source Drain) MOSFET structure which can effectively reduce the GIDL (Gate-Induced Drain Leakage) current is proposed and analyzed. The proposed ESD structure is characterized by sidewall spacer width and recessed-channel depth which are determined by dry-etching process. Elevation of the Source / Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. Unlike the conventional LDD structures, it is shown that the GIDL current of the ESD structure is suppressed without sacrificing the maximum driving capability. The main reason for the reduction of GIDL current is the decreased electric field at the point of the maximum band-to-band tunneling as the peak electric field is shifted toward the drain side. |
キーワード(和) | |
キーワード(英) | self-aligned / ESD MOSFET / GIDL / dry-etching / low-activation effect / peak electric field |
資料番号 | ED2000-46,SDM2000-46 |
発行日 |
研究会情報 | |
研究会 | SDM |
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開催期間 | 2000/6/21(から1日開催) |
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講演論文情報詳細 | |
申込み研究会 | Silicon Device and Materials (SDM) |
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本文の言語 | ENG |
タイトル(和) | |
サブタイトル(和) | |
タイトル(英) | ED2000-46 / SDM2000-46 Analysis of a High Performance Self-Aligned Elevated Source Drain MOSFET with Reduced Gate-Induced Drain-Leakage |
サブタイトル(和) | |
キーワード(1)(和/英) | / self-aligned |
第 1 著者 氏名(和/英) | / Kyung-Whan Kim |
第 1 著者 所属(和/英) | Electrical and Computer Engineering, Yonsei University |
発表年月日 | 2000/6/21 |
資料番号 | ED2000-46,SDM2000-46 |
巻番号(vol) | vol.100 |
号番号(no) | 150 |
ページ範囲 | pp.- |
ページ数 | 6 |
発行日 |