| Presentation | 2000/1/21 High speed, low power and highly reliable sub-0.1um ULSI Shigeyoshi Watanabe, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Design method for 3GHz embedded processor with sub-0.1um design rule has been developed. For realizing this performance, the reduction of the active power, reduction of RC delay time of the wiring, and the improvement of the reliability of the wiring are the key issues. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | GHz operation / embedded MPU / sub-0.1um rule / SOC |
| Paper # | SDM99-182 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2000/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High speed, low power and highly reliable sub-0.1um ULSI |
| Sub Title (in English) | |
| Keyword(1) | GHz operation |
| Keyword(2) | embedded MPU |
| Keyword(3) | sub-0.1um rule |
| Keyword(4) | SOC |
| 1st Author's Name | Shigeyoshi Watanabe |
| 1st Author's Affiliation | Technology Planning Division, Toshiba Corporation() |
| Date | 2000/1/21 |
| Paper # | SDM99-182 |
| Volume (vol) | vol.99 |
| Number (no) | 579 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |