| Presentation | 2000/1/21 Performance Improvement using Triple Damascene Wiring Design Concept for 0.13μm CMOS Devices Noriaki Oda, Akira Matsumoto, Takashi Yokoyama, Takashi Ishigami, Kouichi Motoyama, Noboru Morita, Kazuo Aizawa, Koji Kishimoto, Hideki Gomi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel wiring design concept called "Triple Damascene" is presented. We propose a new technology to mix wirings with different thickness in one layer by using dual damascene process without increasing mask steps. In this technology, three types of grooves are opened simultaneously. Deep trenches for thick wires, as well as vias and shallow trenches, are selectively opened. By the design concept using this technology, a 25% reduction in wiring delay is obtained for critical path. A 5% reduction in chip size is also obtained as the effect of decrease in repeater number for 0.13μm CMOS devices. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Copper / Interconnect / Dual damascene / Design / Wiring delay time |
| Paper # | SDM99-177 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2000/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Improvement using Triple Damascene Wiring Design Concept for 0.13μm CMOS Devices |
| Sub Title (in English) | |
| Keyword(1) | Copper |
| Keyword(2) | Interconnect |
| Keyword(3) | Dual damascene |
| Keyword(4) | Design |
| Keyword(5) | Wiring delay time |
| 1st Author's Name | Noriaki Oda |
| 1st Author's Affiliation | ULSI Device Development Laboratory, NEC Corporation() |
| 2nd Author's Name | Akira Matsumoto |
| 2nd Author's Affiliation | ULSI Device Development Laboratory, NEC Corporation |
| 3rd Author's Name | Takashi Yokoyama |
| 3rd Author's Affiliation | ULSI Device Development Laboratory, NEC Corporation |
| 4th Author's Name | Takashi Ishigami |
| 4th Author's Affiliation | ULSI Device Development Laboratory, NEC Corporation |
| 5th Author's Name | Kouichi Motoyama |
| 5th Author's Affiliation | ULSI Device Development Laboratory, NEC Corporation |
| 6th Author's Name | Noboru Morita |
| 6th Author's Affiliation | VLSI Manufacturing Engineering Division, NEC Corporation |
| 7th Author's Name | Kazuo Aizawa |
| 7th Author's Affiliation | VLSI Manufacturing Engineering Division, NEC Corporation |
| 8th Author's Name | Koji Kishimoto |
| 8th Author's Affiliation | ULSI Device Development Laboratory, NEC Corporation |
| 9th Author's Name | Hideki Gomi |
| 9th Author's Affiliation | ULSI Device Development Laboratory, NEC Corporation |
| Date | 2000/1/21 |
| Paper # | SDM99-177 |
| Volume (vol) | vol.99 |
| Number (no) | 579 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |