Presentation	1999/8/27 Evaluation of Clock Tree Layout in Consideration of Delay Variations Masaaki Azuma, Atsushi Takahashi,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	The increasing speed of the integrated circuit increases the ratio of the delay variation, caused by the temperature and process variations, to the clock period, and it is becoming the major reason of the malfunction. Thus it is important to design a clock tree whose clock arrival time to each register is less affected by the delay variations. We assume that, on a chip, the unit-length clock wire delay varies with a constant gradient. Then we represent the delay variation as the maximum among the defferences between the clock arrival time difference estimated while the design phase and the one with delay variations for all pairs of registers. We studied the effect of delay variations for various clock tree layouts, and give a guide for designing a clock tree which is less affected by the delay variations.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Semi-Synchronous / clock skew / routing delay / delay variation
Paper #	SDM99-127
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Conference Information
Committee	SDM
Conference Date	1999/8/27(1days)
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Paper Information
Registration To	Silicon Device and Materials (SDM)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Evaluation of Clock Tree Layout in Consideration of Delay Variations
Sub Title (in English)
Keyword(1)	Semi-Synchronous
Keyword(2)	clock skew
Keyword(3)	routing delay
Keyword(4)	delay variation
1st Author's Name	Masaaki Azuma
1st Author's Affiliation	Department of Electrical and Electronic Engineering, Tokyo Institute of Technology()
2nd Author's Name	Atsushi Takahashi
2nd Author's Affiliation	Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
Date	1999/8/27
Paper #	SDM99-127
Volume (vol)	vol.99
Number (no)	264
Page	pp.pp.-
#Pages	8
Date of Issue