| Presentation | 1999/7/23 1Gbit DDR SDRAM for Low Voltage and High Speed Application (Invited) Hongil Yoon, Nam Jong Kim, Keum Yong Kim, Sang Jae Rhee, Sang Man Byun, Hyun Suk Lee, Jae Young Lee, Tae Young Ko, Soo In Cho, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A double data rate at 333Mb/s/pin is achieved for a 2.5V 1Gb synchronous DRAM in a 0.14μm process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging and processing technology. Circuit techniques and schemes of ODIC chip with non-ODIC package, cycle-time adaptive wave pipelining, and variable stage analog DLL with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. Double data rate as a viable high-speed and low-voltage DRAM I/O interface is demonstrated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | double data rate (DDR) / delay locked loop (DLL) / phase detector / wave pipeline / low voltage / high speed / DRAM / SDRAM / CMOS |
| Paper # | SDM99-99 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
|---|---|
| Conference Date | 1999/7/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 1Gbit DDR SDRAM for Low Voltage and High Speed Application (Invited) |
| Sub Title (in English) | |
| Keyword(1) | double data rate (DDR) |
| Keyword(2) | delay locked loop (DLL) |
| Keyword(3) | phase detector |
| Keyword(4) | wave pipeline |
| Keyword(5) | low voltage |
| Keyword(6) | high speed |
| Keyword(7) | DRAM |
| Keyword(8) | SDRAM |
| Keyword(9) | CMOS |
| 1st Author's Name | Hongil Yoon |
| 1st Author's Affiliation | Memory Product and Technology Division, Samsung Electronics() |
| 2nd Author's Name | Nam Jong Kim |
| 2nd Author's Affiliation | Memory Product and Technology Division, Samsung Electronics |
| 3rd Author's Name | Keum Yong Kim |
| 3rd Author's Affiliation | Memory Product and Technology Division, Samsung Electronics |
| 4th Author's Name | Sang Jae Rhee |
| 4th Author's Affiliation | Memory Product and Technology Division, Samsung Electronics |
| 5th Author's Name | Sang Man Byun |
| 5th Author's Affiliation | Memory Product and Technology Division, Samsung Electronics |
| 6th Author's Name | Hyun Suk Lee |
| 6th Author's Affiliation | Memory Product and Technology Division, Samsung Electronics |
| 7th Author's Name | Jae Young Lee |
| 7th Author's Affiliation | Memory Product and Technology Division, Samsung Electronics |
| 8th Author's Name | Tae Young Ko |
| 8th Author's Affiliation | Memory Product and Technology Division, Samsung Electronics |
| 9th Author's Name | Soo In Cho |
| 9th Author's Affiliation | Memory Product and Technology Division, Samsung Electronics |
| Date | 1999/7/23 |
| Paper # | SDM99-99 |
| Volume (vol) | vol.99 |
| Number (no) | 232 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |