| Presentation | 1999/6/24 Low-Voltage CMOS Digital Circuits : Present and Future Hiroyuki Mizuno, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes recent low-voltage CMOS digital circuit technology. After clarifying the history of a demand for lower voltage, we review the history of low-voltage circuits with classifying into three categories:(1) Subthreshold leakage current reduction scheme during a standby mode (2) that during an active mode and (3) that with using SOI devices. Finally future perspective is discussed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low-Voltage / Low-Power / CMOS / Subthreshold leakage / Substrate bias |
| Paper # | SDM99-40 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
|---|---|
| Conference Date | 1999/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low-Voltage CMOS Digital Circuits : Present and Future |
| Sub Title (in English) | |
| Keyword(1) | Low-Voltage |
| Keyword(2) | Low-Power |
| Keyword(3) | CMOS |
| Keyword(4) | Subthreshold leakage |
| Keyword(5) | Substrate bias |
| 1st Author's Name | Hiroyuki Mizuno |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| Date | 1999/6/24 |
| Paper # | SDM99-40 |
| Volume (vol) | vol.99 |
| Number (no) | 147 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |