| Presentation | 1999/6/24 A 2-Byte Parallel 1.25 Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking Hideki Takauchi, Kohtaroh Gotoh, Hirotaka Tamura, Tsz shing Cheung, Weixin Gai, Yoichi Koyanagi, Richard Schober, Raghu Sastry, Frank Chen, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An I/O transceiver for scalable multiprocessor systems has been developed with a parallel high bandwith (1.25 Gb/s) and low latency (7.4 ns). We used a phase-interpolator-based clocking scheme that ensures high skew adjustment reolution (25±5 ps adjustment step) and plesiouchronous clocking, which can tolerate slight differences in frequencies between incoming and internal reference clocks. A Differential Partial Response Detection (DPRD) receiver has also been developed to ensure low latency equalization for a skin-effect cable loss up to 10 dB. We designed a test chip for parallel-link interconnection using a 0.25 μm CMOS process, and confirmed a 1.25 Gb/s signal transmission over a 20-m AWG 28 twisted-pair cable. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Interface / Intersymbol interference / CMOS / Clocking |
| Paper # | SDM99-37 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1999/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 2-Byte Parallel 1.25 Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking |
| Sub Title (in English) | |
| Keyword(1) | Interface |
| Keyword(2) | Intersymbol interference |
| Keyword(3) | CMOS |
| Keyword(4) | Clocking |
| 1st Author's Name | Hideki Takauchi |
| 1st Author's Affiliation | Fujitsu Laboratories Ltd.() |
| 2nd Author's Name | Kohtaroh Gotoh |
| 2nd Author's Affiliation | Fujitsu Laboratories Ltd. |
| 3rd Author's Name | Hirotaka Tamura |
| 3rd Author's Affiliation | Fujitsu Laboratories Ltd. |
| 4th Author's Name | Tsz shing Cheung |
| 4th Author's Affiliation | Fujitsu Laboratories Ltd. |
| 5th Author's Name | Weixin Gai |
| 5th Author's Affiliation | HAL Computer Systems |
| 6th Author's Name | Yoichi Koyanagi |
| 6th Author's Affiliation | HAL Computer Systems |
| 7th Author's Name | Richard Schober |
| 7th Author's Affiliation | HAL Computer Systems |
| 8th Author's Name | Raghu Sastry |
| 8th Author's Affiliation | HAL Computer Systems |
| 9th Author's Name | Frank Chen |
| 9th Author's Affiliation | HAL Computer Systems |
| Date | 1999/6/24 |
| Paper # | SDM99-37 |
| Volume (vol) | vol.99 |
| Number (no) | 147 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |