| Presentation | 1999/6/24 110GB/s Simultaneous Bi-directional Transceiver Logic Synchronized with a System Clock Akira Nishida, Tohiro Takahashi, Takashi Muto, Yuji Shirai, Fumihiko Shirotori, Yoshifumi Takada, Akira Yamagiwa, Atsuo Hotta, Tadashi Kiyuna, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A simultaneous bi-directional transceiver logic (SBTL) has been developed for a 0.25μm CMOS ASIC. A low-voltage swing input flip-flop circuit and an output flip-flop circuit with a boundary scan funciton enable a 1.1Gb/s data transfer rate per LSI pin. An output buffer with a slew rate control function and a 1595-pin ceramic surface-mount type PGA package with on-package capacitors achieve 100-byte data bus per LSI. The maximum data bandwidth per LSI is 110GB/s. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS ASIC / Boundary Scan / PLL / Multi-cycle transmission / 1595-pin PGA package |
| Paper # | SDM99-36 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1999/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 110GB/s Simultaneous Bi-directional Transceiver Logic Synchronized with a System Clock |
| Sub Title (in English) | |
| Keyword(1) | CMOS ASIC |
| Keyword(2) | Boundary Scan |
| Keyword(3) | PLL |
| Keyword(4) | Multi-cycle transmission |
| Keyword(5) | 1595-pin PGA package |
| 1st Author's Name | Akira Nishida |
| 1st Author's Affiliation | Hitachi ULSI Systems Co., Ltd.() |
| 2nd Author's Name | Tohiro Takahashi |
| 2nd Author's Affiliation | Hitachi Ltd. |
| 3rd Author's Name | Takashi Muto |
| 3rd Author's Affiliation | Hitachi Ltd. |
| 4th Author's Name | Yuji Shirai |
| 4th Author's Affiliation | Hitachi Ltd. |
| 5th Author's Name | Fumihiko Shirotori |
| 5th Author's Affiliation | Hitachi Ltd. |
| 6th Author's Name | Yoshifumi Takada |
| 6th Author's Affiliation | Hitachi Ltd. |
| 7th Author's Name | Akira Yamagiwa |
| 7th Author's Affiliation | Hitachi Ltd. |
| 8th Author's Name | Atsuo Hotta |
| 8th Author's Affiliation | Hitachi ULSI Systems Co., Ltd. |
| 9th Author's Name | Tadashi Kiyuna |
| 9th Author's Affiliation | Hitachi Information Technology Co., Ltd. |
| Date | 1999/6/24 |
| Paper # | SDM99-36 |
| Volume (vol) | vol.99 |
| Number (no) | 147 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |