| Presentation | 1999/6/24 A compact 54×54-bit Multiplier with Improved Wallace-Tree Structure Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an efficient layout method for high-speed 54×54-bit multiplier. Wallace-Tree method is generally adopted to the high-speed multiplier. In the conventional Wallace-Tree, however, every partial product is added in a single direction from top to bottom. Therefore, the necessary number of adders increases as the adding stage moves forward. As a result, it generates a dead area when multiplier is arranged in rectangle. To solve this problem, we propose a new Wallace-Tree construction method. In our method, the partial products are divided in to two groups and added to the opposite direciton. One is added to downward, and the other is added to upward. Using this method, we can eliminate the dead area. Also our method can simplify the layout. The 980μm×1000μm area size and the 600 MHz clock speed have been achieved using 0.18μm CMOS Technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Wallace-Tree / multiplier / critical path / computer graphics / high speed / CMOS |
| Paper # | SDM99-30 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
|---|---|
| Conference Date | 1999/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A compact 54×54-bit Multiplier with Improved Wallace-Tree Structure |
| Sub Title (in English) | |
| Keyword(1) | Wallace-Tree |
| Keyword(2) | multiplier |
| Keyword(3) | critical path |
| Keyword(4) | computer graphics |
| Keyword(5) | high speed |
| Keyword(6) | CMOS |
| 1st Author's Name | Niichi Itoh |
| 1st Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation() |
| 2nd Author's Name | Yuka Naemura |
| 2nd Author's Affiliation | LSI Design Center, Mitsubishi Electric Engineering Company Limited |
| 3rd Author's Name | Hiroshi Makino |
| 3rd Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
| 4th Author's Name | Yasunobu Nakase |
| 4th Author's Affiliation | System LSI Development Center, Mitsubishi Electric Corporation |
| Date | 1999/6/24 |
| Paper # | SDM99-30 |
| Volume (vol) | vol.99 |
| Number (no) | 147 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |