| Presentation | 1994/12/15 Block-Independent Redundant Cell Array Scheme for 256Mb DRAM Atsushi Hatakeyama, Masato Matsumiya, Toshiya Uchida, Tadao Aikawa, Shinya Fujioka, Shuusaku Yamaguchi, Makoto Koga, Masao Taguchi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 256M-bit DRAM designed for high redundant cell efficiency was developed.Defective rows or columns in any cell blocks could be replaced by the redundant cell array with sense amplifiers.A part of DQs are replaceable resulting in the redundant unit size minimum.Two sets of redundant cell arrays are prepared in order to replace two defects in an actived block,which also relieves a. defect in the redundant cell array. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 256M / DRAM / Redundancy / Multibit / High speed |
| Paper # | SDM94-158,ICD94-161 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1994/12/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Block-Independent Redundant Cell Array Scheme for 256Mb DRAM |
| Sub Title (in English) | |
| Keyword(1) | 256M |
| Keyword(2) | DRAM |
| Keyword(3) | Redundancy |
| Keyword(4) | Multibit |
| Keyword(5) | High speed |
| 1st Author's Name | Atsushi Hatakeyama |
| 1st Author's Affiliation | Memory LSI Design Division,Fujitsu Laboratory() |
| 2nd Author's Name | Masato Matsumiya |
| 2nd Author's Affiliation | Memory LSI Design Division,Fujitsu Laboratory |
| 3rd Author's Name | Toshiya Uchida |
| 3rd Author's Affiliation | Memory LSI Design Division,Fujitsu Laboratory |
| 4th Author's Name | Tadao Aikawa |
| 4th Author's Affiliation | Memory LSI Design Division,Fujitsu Laboratory |
| 5th Author's Name | Shinya Fujioka |
| 5th Author's Affiliation | Memory LSI Design Division,Fujitsu Laboratory |
| 6th Author's Name | Shuusaku Yamaguchi |
| 6th Author's Affiliation | Memory LSI Design Division,Fujitsu Laboratory |
| 7th Author's Name | Makoto Koga |
| 7th Author's Affiliation | Memory LSI Design Division,Fujitsu Laboratory |
| 8th Author's Name | Masao Taguchi |
| 8th Author's Affiliation | Memory LSI Design Division,Fujitsu Laboratory |
| Date | 1994/12/15 |
| Paper # | SDM94-158,ICD94-161 |
| Volume (vol) | vol.94 |
| Number (no) | 406 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |