Presentation 1994/5/27
A 220MHz Pipeline 16Mb BiCMOS SRAM with PLL Proportional Self- Timing Generator
Shigeru Kuhara, Kazuyuki Nakamura, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This 16Mb Synchronous BiCMOS SRAM achives 22OMHz operation with GTL interface,using a 2-stage wave-pipeline operation and a PLL Self-Timing generator.Developed circuit technologies to realize the wave-pipeline operation are 1-a)a Zigzag double-word line layout scheme and 1-b)a centered bit-line load layout scheme. Forthermore,2-a)our PLL has voltage controlled oscillator(VCO), which contains a multi-stage tapped ring-oscillator.This VCO can generate a clock cycle proportional pulse(CCPP)and a clock edge lookahead pulse(CELP).
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SRAM / Bi CMOS / High-speed memory / PLL / パイプライン / GTL
Paper # SDM94-32,ICD94-43
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Conference Information
Committee SDM
Conference Date 1994/5/27(1days)
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Paper Information
Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 220MHz Pipeline 16Mb BiCMOS SRAM with PLL Proportional Self- Timing Generator
Sub Title (in English)
Keyword(1) SRAM
Keyword(2) Bi CMOS
Keyword(3) High-speed memory
Keyword(4) PLL
Keyword(5) パイプライン
Keyword(6) GTL
1st Author's Name Shigeru Kuhara
1st Author's Affiliation NEC()
2nd Author's Name Kazuyuki Nakamura
2nd Author's Affiliation NEC
3rd Author's Name Tohru Kimura
3rd Author's Affiliation NEC
4th Author's Name Masahide Takada
4th Author's Affiliation NEC
5th Author's Name Hisamitsu Suzuki
5th Author's Affiliation NEC
6th Author's Name Hiroshi Yoshida
6th Author's Affiliation NEC
7th Author's Name Tohru Yamazaki
7th Author's Affiliation NEC
Date 1994/5/27
Paper # SDM94-32,ICD94-43
Volume (vol) vol.94
Number (no) 73
Page pp.pp.-
#Pages 8
Date of Issue