Presentation 1994/5/27
3.3V single power-supply 64Mb-flash memory with dynamic bit- latch(DBL) programming scheme
Toshio Takeshima, Hiroshi Sugawara, Hiroshi Takada, Yoshiaki Hisamune, Kohji Kanamori, Takeshi Okazawa, Tatsunori Murotani, Isao Sasaki,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 3.3 V single power-supply 64M bit flash memory has been developed by using 0.4 ym CMOS technology.50 ns access time and 256-bit erase, programming unitcapacity have been achieved by using hierarchical word-line and bit-line structure.Dynamic Bit- line Latch(DBL)programming scheme,which enables 256 bit simultaneous programming,has been developed.The chip measures 19.3 mm by 13.3 mm.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) flash memory / 64M bit / multi-bit programming / data register / hierarchical structure
Paper # SDM94-29,ICD94-40
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Conference Information
Committee SDM
Conference Date 1994/5/27(1days)
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Paper Information
Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 3.3V single power-supply 64Mb-flash memory with dynamic bit- latch(DBL) programming scheme
Sub Title (in English)
Keyword(1) flash memory
Keyword(2) 64M bit
Keyword(3) multi-bit programming
Keyword(4) data register
Keyword(5) hierarchical structure
1st Author's Name Toshio Takeshima
1st Author's Affiliation NEC()
2nd Author's Name Hiroshi Sugawara
2nd Author's Affiliation NEC
3rd Author's Name Hiroshi Takada
3rd Author's Affiliation NEC
4th Author's Name Yoshiaki Hisamune
4th Author's Affiliation NEC
5th Author's Name Kohji Kanamori
5th Author's Affiliation NEC
6th Author's Name Takeshi Okazawa
6th Author's Affiliation NEC
7th Author's Name Tatsunori Murotani
7th Author's Affiliation NEC
8th Author's Name Isao Sasaki
8th Author's Affiliation NEC
Date 1994/5/27
Paper # SDM94-29,ICD94-40
Volume (vol) vol.94
Number (no) 73
Page pp.pp.-
#Pages 6
Date of Issue