Presentation | 1998/5/22 DLTS study of 3C-SiC grown on Si substrates : Defects observable above room temperature M. Kato, Y. Koga, M. Ichimura, E. Arai, N. Yamada, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | n-type 3C-SiC was grown on Si(100) substrates by chemical vapor deposition. In order to observe defects located near the middle of the band gap, the DLTS measurement was carried out in a temperature range from 100K to 600K. A DLTS peak appeared near 150K for all the samples. Some samples showed a peak near room temperature, but the width and position of this peak were different between samples. One of the samples showed a broad peak near 500K. This peak was attributed to deep defects whose activation energy is in the range of 1.07-1.35eV. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | 3C-SiC / DLTS / deep level |
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Conference Information | |
Committee | SDM |
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Conference Date | 1998/5/22(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Silicon Device and Materials (SDM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | DLTS study of 3C-SiC grown on Si substrates : Defects observable above room temperature |
Sub Title (in English) | |
Keyword(1) | 3C-SiC |
Keyword(2) | DLTS |
Keyword(3) | deep level |
1st Author's Name | M. Kato |
1st Author's Affiliation | Nagoya Inst.Tech() |
2nd Author's Name | Y. Koga |
2nd Author's Affiliation | Nagoya Inst.Tech |
3rd Author's Name | M. Ichimura |
3rd Author's Affiliation | Nagoya Inst.Tech |
4th Author's Name | E. Arai |
4th Author's Affiliation | Nagoya Inst.Tech |
5th Author's Name | N. Yamada |
5th Author's Affiliation | Toyota Central Lab. |
Date | 1998/5/22 |
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Volume (vol) | vol.98 |
Number (no) | 64 |
Page | pp.pp.- |
#Pages | 6 |
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