| Presentation | 1998/4/24 『Shallow Source/Drain Extensions for pMOSFETs with High Activation and Low Process Damage Fabricated by Plasma Doping』 Michihiko TAKASE, Kyoji YAMASHITA, Atsushi HORI, Bunji MIZUNO, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Low sheet resistance and extremely shallow profiles are achived by plasma doping with low process damage and high activation efficiency.High performance pMOSFETs have been also fabricated by taking advantage of well-controlled plasma doped extensions.Linear trans-conductance(Gm)of the pMOSFET with plasma doped extensions is about 30% larger than that of 10 keV ion implanted device with same source/drain junction depth. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | plasma doping / shallow junction / high activation / parasitic series resistance / pMOSFET / source/drain extension |
| Paper # | |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
|---|---|
| Conference Date | 1998/4/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 『Shallow Source/Drain Extensions for pMOSFETs with High Activation and Low Process Damage Fabricated by Plasma Doping』 |
| Sub Title (in English) | |
| Keyword(1) | plasma doping |
| Keyword(2) | shallow junction |
| Keyword(3) | high activation |
| Keyword(4) | parasitic series resistance |
| Keyword(5) | pMOSFET |
| Keyword(6) | source/drain extension |
| 1st Author's Name | Michihiko TAKASE |
| 1st Author's Affiliation | Central Research Laboratory, Matsushita Electric Ind., Co., Ltd.() |
| 2nd Author's Name | Kyoji YAMASHITA |
| 2nd Author's Affiliation | ULSI Process Technology Development Center, Matsushita Electronics Corporation |
| 3rd Author's Name | Atsushi HORI |
| 3rd Author's Affiliation | ULSI Process Technology Development Center, Matsushita Electronics Corporation |
| 4th Author's Name | Bunji MIZUNO |
| 4th Author's Affiliation | Central Research Laboratory, Matsushita Electric Ind., Co., Ltd. |
| Date | 1998/4/24 |
| Paper # | |
| Volume (vol) | vol.98 |
| Number (no) | 31 |
| Page | pp.pp.- |
| #Pages | 7 |
| Date of Issue | |