| Presentation | 1998/4/24 Vertical Sub-100nm MOSFETs Hansch W, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The fabrication of vertical sub-100nm MOSFETs by using optical lithography is demonstrated.Significant improvements in terms of avalanche suppression, current and speed are achievable in such MOSFETs by employing a planar-doped barrier MOSFET(PDBFET).The tailoring of electric fields by delta-doping leads to the realization of carrier velocity overshoot, a change in velocity distribution from Maxwellian to Gaussian and a proposed model of carrier density quantization at low temperatures.Yield of about 70% and reproducibility of fabricated devices in terms of leakage current, threshold voltage and transconductance of about σ～3% on chips and 10% over the wafer are observed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Vertical sub-100nm MOSFETs / velocity overshoot / avalanche suppression / carrier density quantization / yield |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1998/4/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Vertical Sub-100nm MOSFETs |
| Sub Title (in English) | |
| Keyword(1) | Vertical sub-100nm MOSFETs |
| Keyword(2) | velocity overshoot |
| Keyword(3) | avalanche suppression |
| Keyword(4) | carrier density quantization |
| Keyword(5) | yield |
| 1st Author's Name | Hansch W |
| 1st Author's Affiliation | Research Center for Nanodevices and Systems Hiroshima University() |
| Date | 1998/4/24 |
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| Volume (vol) | vol.98 |
| Number (no) | 31 |
| Page | pp.pp.- |
| #Pages | 8 |
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