| Presentation | 1998/4/23 Electrical Conduction of Double-Barrier Ultrasmall MOS Transistors Tsuyoshi HATANO, Akihiro NOMURA, Masayoshi YOSHIDA, Anri NAKAJIMA, Kentaro SHIBAHARA, Shin YOKOYAMA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Novel ultrasmall MOS transistors with double potential barriers are proposed.The structure is similar to the LDD (Lightly Doped Drain) MOS transistors with two gates.The double potential barriers are formed under the side wall spacers, which are controlled by the upper gate voltage.It is necessary that the double potential barriers, through which the tunneling current is larger than the thermal excited current, is formed, in order to operate at room temperature.It is confirmed that the double potential barriers are formed.The tunnelng current is suppressed in the vicinity of zero drain voltage by the Coulomb blockade effect.The thermal excited current is smaller than the tunneling current when high substrate doping concentration is employed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | depletion-layer barrier / room temperature Coulomb blockade / tunneling current / thermal excited current / substrate doping concentration |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1998/4/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Electrical Conduction of Double-Barrier Ultrasmall MOS Transistors |
| Sub Title (in English) | |
| Keyword(1) | depletion-layer barrier |
| Keyword(2) | room temperature Coulomb blockade |
| Keyword(3) | tunneling current |
| Keyword(4) | thermal excited current |
| Keyword(5) | substrate doping concentration |
| 1st Author's Name | Tsuyoshi HATANO |
| 1st Author's Affiliation | Reserch Center for Nanodevices and Systems, Hiroshima University() |
| 2nd Author's Name | Akihiro NOMURA |
| 2nd Author's Affiliation | Reserch Center for Nanodevices and Systems, Hiroshima University |
| 3rd Author's Name | Masayoshi YOSHIDA |
| 3rd Author's Affiliation | Reserch Center for Nanodevices and Systems, Hiroshima University |
| 4th Author's Name | Anri NAKAJIMA |
| 4th Author's Affiliation | Reserch Center for Nanodevices and Systems, Hiroshima University |
| 5th Author's Name | Kentaro SHIBAHARA |
| 5th Author's Affiliation | Reserch Center for Nanodevices and Systems, Hiroshima Univeristy |
| 6th Author's Name | Shin YOKOYAMA |
| 6th Author's Affiliation | Reserch Center for Nanodevices and Systems, Hiroshima University |
| Date | 1998/4/23 |
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| Volume (vol) | vol.98 |
| Number (no) | 30 |
| Page | pp.pp.- |
| #Pages | 5 |
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