| Presentation | 1993/11/26 High-Speed,small-amplitude interface circuits for memory bus application Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Seiichi Saitoh, Noriyuki Matsui, Shigeru Takamura, Tatsuo Koizumi, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | High performance I, O circuits for fast memory devices such as Synchronous DRAM were investigated.For TTL interface,the capacitive loading must increase as the I/O speeds are increased, and signal termination is necessary for signal transmission speeds of over 100MHz.For this reason,industry proposed alternative interface approaches such as GTL and CTT were investigated using experimental test devices.GTL standard was found to have a problem that,as the frequency increases,there is degradation of output high voltage.The problem was traced backed to signal reflection occuring in the region of impedance mismatch.Terminated LVTTL(T- LVTTL)circuit is proposed as an approach more suitable for high speed data transfer. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Interface / I/O Scircuit / Synchronous DRAM |
| Paper # | SDM93-149,ICD93-143 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1993/11/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Speed,small-amplitude interface circuits for memory bus application |
| Sub Title (in English) | |
| Keyword(1) | Interface |
| Keyword(2) | I/O Scircuit |
| Keyword(3) | Synchronous DRAM |
| 1st Author's Name | Masao Taguchi |
| 1st Author's Affiliation | Memory LSI Design Division,Fujitsu() |
| 2nd Author's Name | Satoshi Eto |
| 2nd Author's Affiliation | Memory LSI Design Division,Fujitsu |
| 3rd Author's Name | Yoshihiro Takemae |
| 3rd Author's Affiliation | Memory LSI Design Division,Fujitsu |
| 4th Author's Name | Seiichi Saitoh |
| 4th Author's Affiliation | Common Technology Division,Fujitsu |
| 5th Author's Name | Noriyuki Matsui |
| 5th Author's Affiliation | Common Technology Division,Fujitsu |
| 6th Author's Name | Shigeru Takamura |
| 6th Author's Affiliation | Common Technology Division,Fujitsu |
| 7th Author's Name | Tatsuo Koizumi |
| 7th Author's Affiliation | Common Technology Division,Fujitsu |
| Date | 1993/11/26 |
| Paper # | SDM93-149,ICD93-143 |
| Volume (vol) | vol.93 |
| Number (no) | 349 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |