Presentation 1993/11/26
Two-dimensional power-line selection scheme for low subthreshold- current multi-gigabit DRAMs
Takeshi Sakata, Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Two-dimensional power-line selection scheme for an iterative CMOS circuit block,is proposed to reduce the subthreshold current. In this scheme,a block is divided into subblocks of two- dimensional arrangement and selectively energized by two- dimensional power-line selection.The scheme combined with dual word-line structure permits a drastic active current reduction to one sixteenth,from 363 mA to 22 mA,for a 16-Gb DRAM.
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Keyword(in English) DRAM / gigabit / threshold voltage / subthreshold current / two dimensional / power line
Paper # SDM93-147,ICD93-141
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Conference Information
Committee SDM
Conference Date 1993/11/26(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Two-dimensional power-line selection scheme for low subthreshold- current multi-gigabit DRAMs
Sub Title (in English)
Keyword(1) DRAM
Keyword(2) gigabit
Keyword(3) threshold voltage
Keyword(4) subthreshold current
Keyword(5) two dimensional
Keyword(6) power line
1st Author's Name Takeshi Sakata
1st Author's Affiliation Central Research Laboratory,Hitachi()
2nd Author's Name Masashi Horiguchi
2nd Author's Affiliation Central Research Laboratory,Hitachi
3rd Author's Name Masakazu Aoki
3rd Author's Affiliation Central Research Laboratory,Hitachi
4th Author's Name Kiyoo Itoh
4th Author's Affiliation Central Research Laboratory,Hitachi
Date 1993/11/26
Paper # SDM93-147,ICD93-141
Volume (vol) vol.93
Number (no) 349
Page pp.pp.-
#Pages 6
Date of Issue