| Presentation | 1993/11/26 250Mbyte/sec Synchronous DRAM using a 3-Stage-pipelined Architecture Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzou, Hiroshi Watanabe, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 3.3-v 512k×18bit×2-bank synchronous DRAM(SDRAM)has been devel oped using a novel 3-stage-pipelined architecture.The address- access path which is usually designed by analog means,is digitized, separated into three stages by latch circuits at the column switch and data-out buffer.Since this architecture requires no additional read, write bus and data amp,it minimizes an increase in die size. Using the standardized GTL interface,a 250-Mbyte/sec synchronous DRAM with die size of 113.7-mm^2,which is the same die-size as our conventional DRAM,has been acheved with 0.50μ m CMOS process techn ology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 16Mbit DRAM / Synchronous DRAM / pipelined architecture |
| Paper # | SDM93-142,ICD93-136 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1993/11/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 250Mbyte/sec Synchronous DRAM using a 3-Stage-pipelined Architecture |
| Sub Title (in English) | |
| Keyword(1) | 16Mbit DRAM |
| Keyword(2) | Synchronous DRAM |
| Keyword(3) | pipelined architecture |
| 1st Author's Name | Yasuhiro Takai |
| 1st Author's Affiliation | NEC() |
| 2nd Author's Name | Mamoru Nagase |
| 2nd Author's Affiliation | NEC Electronics Singapore |
| 3rd Author's Name | Mamoru Kitamura |
| 3rd Author's Affiliation | NEC |
| 4th Author's Name | Yasuji Koshikawa |
| 4th Author's Affiliation | NEC |
| 5th Author's Name | Naoyuki Yoshida |
| 5th Author's Affiliation | NEC |
| 6th Author's Name | Yasuaki Kobayashi |
| 6th Author's Affiliation | NEC IC Maicrocomputer Systems,Ltd |
| 7th Author's Name | Takashi Obara |
| 7th Author's Affiliation | NEC |
| 8th Author's Name | Yukio Fukuzou |
| 8th Author's Affiliation | NEC |
| 9th Author's Name | Hiroshi Watanabe |
| 9th Author's Affiliation | NEC |
| Date | 1993/11/26 |
| Paper # | SDM93-142,ICD93-136 |
| Volume (vol) | vol.93 |
| Number (no) | 349 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |