| Presentation | 1993/11/26 A 4.4Mbit Triple Port VRAM for Mlutimedia Tetsuyuki Fukushima, Akifumi Kawahara, Ryoutaro Azuma, Kazuyosi Nishi, Akihiro Matsumoto, Katsumi Wada, Tomonori Kataoka, Toshiki Mori, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A pixel(bit)aligned VRAM architecture and new circuit technologies are described for a 4.4Mb Triple-port DRAM that has a 270K word x 16b Random Access Memory(RAM),a 512 word x 8b Serial Access Memory-(a)(SAMa)and a 1024 word x 4b Serial Access Memory- (b)(SAMb).The random port,serial-a and serial-b port can be operated by three independent synchronous clocks.In these three ports,word data can be aligned to the location of an arbitrary bit position.Data transfer from SAMb to RAM can be individually masked by transfer mask data.The RAM operates by 33MHz synchronous clock and two SAMs operate by 40MHz clocks. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | VRAM / Triple-port / Pixel-Align / Charge-Share / Sense- Amplifier-Driver |
| Paper # | SDM93-141,ICD93-135 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 1993/11/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 4.4Mbit Triple Port VRAM for Mlutimedia |
| Sub Title (in English) | |
| Keyword(1) | VRAM |
| Keyword(2) | Triple-port |
| Keyword(3) | Pixel-Align |
| Keyword(4) | Charge-Share |
| Keyword(5) | Sense- Amplifier-Driver |
| 1st Author's Name | Tetsuyuki Fukushima |
| 1st Author's Affiliation | VLSI Device Laboratory Semiconductor Research Center Matsushita Electric Industrial Co.,Ltd.,() |
| 2nd Author's Name | Akifumi Kawahara |
| 2nd Author's Affiliation | VLSI Device Laboratory Semiconductor Research Center Matsushita Electric Industrial Co.,Ltd., |
| 3rd Author's Name | Ryoutaro Azuma |
| 3rd Author's Affiliation | VLSI Device Laboratory Semiconductor Research Center Matsushita Electric Industrial Co.,Ltd., |
| 4th Author's Name | Kazuyosi Nishi |
| 4th Author's Affiliation | VLSI Device Laboratory Semiconductor Research Center Matsushita Electric Industrial Co.,Ltd., |
| 5th Author's Name | Akihiro Matsumoto |
| 5th Author's Affiliation | Memory Development Department Memory Devision Matsushita Electronics Co. |
| 6th Author's Name | Katsumi Wada |
| 6th Author's Affiliation | Memory Development Department Memory Devision Matsushita Electronics Co. |
| 7th Author's Name | Tomonori Kataoka |
| 7th Author's Affiliation | VLSI Derice Laboratory Semiconductor Research Center Matsushita Electric Industrial Co.,Ltd. |
| 8th Author's Name | Toshiki Mori |
| 8th Author's Affiliation | VLSI Derice Laboratory Semiconductor Research Center Matsushita Electric Industrial Co.,Ltd. |
| Date | 1993/11/26 |
| Paper # | SDM93-141,ICD93-135 |
| Volume (vol) | vol.93 |
| Number (no) | 349 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |