| Presentation | 1993/7/26 Interface-Trap Evaluation for Ultra-Thin Gate Oxide MOS Capacitors: Oxide Thickness Dependence of the Si-SiO_2 Interface-Trap Generation under -Bt Aging Shigeo Ogawa, Masakazu Shimaya, Noboru Shiono, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have evaluated interface-trap density(D_it>)distributions at the Si-SiO_2 interface for ultra-thin(4.2nm-thick)gate-oxide metal- oxide-semiconductor(MOS)diodes by the small signal conductance technique.The conventional quasi-static capacitance-voltage technique cannot be used to such thin-oxide samples because of tunneling currents through the oxide.In the technique,D_it> is detected as the frequency-dependent equivalent parallel conductance,which is separable from frequency-independent background losses due to the oxide leak.The method was applied to characterize the D_it>,generation at the Si-SiO_2 interface of ultra-thin oxide MOS diodes subjected to negative-bias-temperature aging stresses.The D_it>,generation is shown to be strongly affected by stress-bias and temperature,and to have weak oxide- thickness dependence.These results show that thin-oxide MOS structures are mainly degraded by the D_it>,generation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ultra-Thin Gate-Oxide MOS / Interface-Trap Evaluation / Conductance Technique / -BT Aging Stress / Oxide-Thickness Dependence / Si-SiO_2 Interface |
| Paper # | SDM93-65 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1993/7/26(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Interface-Trap Evaluation for Ultra-Thin Gate Oxide MOS Capacitors: Oxide Thickness Dependence of the Si-SiO_2 Interface-Trap Generation under -Bt Aging |
| Sub Title (in English) | |
| Keyword(1) | Ultra-Thin Gate-Oxide MOS |
| Keyword(2) | Interface-Trap Evaluation |
| Keyword(3) | Conductance Technique |
| Keyword(4) | -BT Aging Stress |
| Keyword(5) | Oxide-Thickness Dependence |
| Keyword(6) | Si-SiO_2 Interface |
| 1st Author's Name | Shigeo Ogawa |
| 1st Author's Affiliation | NTT LSI Laboratories() |
| 2nd Author's Name | Masakazu Shimaya |
| 2nd Author's Affiliation | NTT LSI Laboratories |
| 3rd Author's Name | Noboru Shiono |
| 3rd Author's Affiliation | NTT LSI Laboratories |
| Date | 1993/7/26 |
| Paper # | SDM93-65 |
| Volume (vol) | vol.93 |
| Number (no) | 172 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |