Presentation 1993/7/26
The Effect of High Voltage Stress on Poly Si MOSTFT
Alberto O. ADN, Motoharu Arimura,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Hot-carrier effects in PolySi PMOS Ms,for SRM application,have been investigated.Devices stressed in the OFF state at Vds>7v,show more than 1, 10 reduction of the leakage(IOFF)current,and suppression of the Gate Induced Drain Leakage(GIDL).kmealing at 400℃ recovers the device characteristics to the pre-stress values. Correlation of the hot-carrier effects,leakage current mechanism and gate current are demonstrated.The increase of the gate current follows the increase of drain OFF current with drain voltage, determined by band-to-band tunneling in the gate-drain overlap region.IOFF reduction and GIDL suppression are caused by hot- electron trapping in the gate oxide,am this phenomena is supported bv the correlation with the measured gate current.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) PolySi / TFT / SRAM / Hot-Carrier
Paper # SDM93-62
Date of Issue

Conference Information
Committee SDM
Conference Date 1993/7/26(1days)
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Paper Information
Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) The Effect of High Voltage Stress on Poly Si MOSTFT
Sub Title (in English)
Keyword(1) PolySi
Keyword(2) TFT
Keyword(3) SRAM
Keyword(4) Hot-Carrier
1st Author's Name Alberto O. ADN
1st Author's Affiliation IC Group VLSI Research lab.,SHARP()
2nd Author's Name Motoharu Arimura
2nd Author's Affiliation IC Group VLSI Research lab.,SHARP
Date 1993/7/26
Paper # SDM93-62
Volume (vol) vol.93
Number (no) 172
Page pp.pp.-
#Pages 8
Date of Issue