| Presentation | 1995/10/20 Estimation of yield suppression for Gigabit DRAMs caused by Vt variation due to fluctuation in dopant distributions Shigeyoshi Watanabe, Takaaki Minami, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper newly estimates the yield suppression for 1.5V 1Gbit DRAM caused by Vt variation of MOSFET due to macroscopic fluctuations in dopant distributions within a channel region. Further-more, the novel optimized redundancy techniques for enhancing the yield is proposed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 1Gbit DRAM / yield / Vt variation |
| Paper # | SDM95-154 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 1995/10/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Estimation of yield suppression for Gigabit DRAMs caused by Vt variation due to fluctuation in dopant distributions |
| Sub Title (in English) | |
| Keyword(1) | 1Gbit DRAM |
| Keyword(2) | yield |
| Keyword(3) | Vt variation |
| 1st Author's Name | Shigeyoshi Watanabe |
| 1st Author's Affiliation | ULSI Research Laboratories, Research and development Center, Toshiba Corporation() |
| 2nd Author's Name | Takaaki Minami |
| 2nd Author's Affiliation | Semiconductor Group, Toshiba Corporation |
| Date | 1995/10/20 |
| Paper # | SDM95-154 |
| Volume (vol) | vol.95 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |