| Presentation | 1996/3/11 Development of Sub-Quarter-μm MONOS Type Memory Transistor : Effect of Rapid Thermal Anneal on Bottom SiO_2 Machio Yamagishi, Akihiro Nakamura, Hiroshi Aozasa, Yasutoshi Komatsu, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A MONOS(metal/oxide/nitride/oxide/semiconductor)type nonvolatile memory transistor with a gate length of 0.23μm has been developed. This memory transistor offers high endurance, low programming voltage and a narrow distribution of programmed threshoid voltage. By introducing a rapid thermal nitridation(RTN) step lnto the fabrication process of the ONO(oxide/nitride/oxide)layer, an enhancement in erase speed of one order of magnitude is achieved. The RTN also improves the oxidation resistance of the nitride layer, so that scaling down the thickness of the ONO film in order to reduce the programming voltage is feasible. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MONOS / nonvolatile memory / ONO / RTN / sub-quarter-μm |
| Paper # | SDM95-268 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
|---|---|
| Conference Date | 1996/3/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Sub-Quarter-μm MONOS Type Memory Transistor : Effect of Rapid Thermal Anneal on Bottom SiO_2 |
| Sub Title (in English) | |
| Keyword(1) | MONOS |
| Keyword(2) | nonvolatile memory |
| Keyword(3) | ONO |
| Keyword(4) | RTN |
| Keyword(5) | sub-quarter-μm |
| 1st Author's Name | Machio Yamagishi |
| 1st Author's Affiliation | Advanced Devices Department, ULSI R&D Laboratories Semiconductor Company Atsugi Technology Center, Sony Corporation() |
| 2nd Author's Name | Akihiro Nakamura |
| 2nd Author's Affiliation | Advanced Devices Department, ULSI R&D Laboratories Semiconductor Company Atsugi Technology Center, Sony Corporation |
| 3rd Author's Name | Hiroshi Aozasa |
| 3rd Author's Affiliation | Advanced Devices Department, ULSI R&D Laboratories Semiconductor Company Atsugi Technology Center, Sony Corporation |
| 4th Author's Name | Yasutoshi Komatsu |
| 4th Author's Affiliation | Advanced Devices Department, ULSI R&D Laboratories Semiconductor Company Atsugi Technology Center, Sony Corporation |
| Date | 1996/3/11 |
| Paper # | SDM95-268 |
| Volume (vol) | vol.95 |
| Number (no) | 570 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |